1. Field of the Invention
The present invention relates to a video signal processing apparatus useful for converting analog input video signals into binary signals employing dither coding.
2. Description of the Prior Arts
Image transmission and recording systems such as facsimile have a problem in particular when the output form is of a black or white binary recording type. This type of transmission system is suitable for character transmission but unsuitable for transmission of a photograph containing halftone.
To solve the problem, hitherto, a method commonly called systematic dither coding has been used. According to the known method, an original picture area is divided into a plural number of picture element groups each group containing about 4 to 32 picture elements. Binary encoding is carried out using a threshold level which is periodically variable for every group. Halftone is represented as the area of black spots gathered in every picture element group.
According to the above mentioned method, an original may be reproduced in many gradations the number of which can be infinite in principle. However, if it is desired to represent very fine gradation, then the number of picture elements in every group necessary for representation of the fine gradation increases up and therefore the dither matrix becomes large to such extent that the quasi halftone screen is too coarse to be acceptable. The reproduction thus obtained is illegible. This is a drawback of the apparatus. When an original containing both characters and a photopicture is to be transmitted, the use of systematic dither brings forth another problem. Although the gradation of the picture can be correctly transmitted, the character portion of the original is transmitted poorly and reproduced illegibly. On the contrary, if the binary encoding is carried out with the threshold level being fixed, the picture portion will be defeatured while the character portion can be transmitted well. These defects contradict each other.
FIG. 1 shows a form of the systematic dither circuit according to the prior art. For the purpose of simplification, description is made in connection with a representation of images in four gradations.
In FIG. 1, reference character 1 designates a video signal input terminal through which analog signals are introduced into the circuit. Element 2 is an A-D converter by which the input video signals are quantized. Element 3 designates the signal line for the digital video signals from the A-D converter. The number of bits for quantization is a whole number (n) which is given by: EQU 2.sup.n .gtoreq.N
wherein, N is the required number of gradations of density (blackness). For instance, when it is required to represent the image density in sixteen (16) gradations, then the number of bits for quantization is 4 bits. For purposes of illustration, signal lines having the same function are represented by the single lines using the symbol " " in FIG. 1. Therefore, it should be understood that the signal line indicated by the symbol may represent a number of signal lines. This is applied also to the following drawings.
Designated by 4 is a magnitude comparator by which signals on a comparison signal line (hereinafter referred to as dither signal line) are binary compared regarding magnitude. The result is put out from the video signal output terminal 5. The video signal output 5 is a binary signal, that is 0 or 1. Elements 7, 8, 9 and 10 are preset switches for setting dither motors. By selecting the preset dither motor and starting reading there is formed a dither signal 6. This selection is carried out by a data selector 11. The output signal from the data selector, therefore, constitutes the dither signal 6. The sequence in which the preset switches are changed over, is controlled by horizontal and vertical address control lines 16 and 17.
Element 12 is a video transfer clock signal, 3 is a horizontal counter, 14 is a horizontal synchronizing signal and 15 is a vertical counter. Since the dither matrix is desirable to be square, the number of bits y of the horizontal address control line 16 is equal to the number of bits x of the vertical address control line 17. In the shown example, by setting the bit to x=y=1, there can be formed a square dither matrix of EQU 2.times.2=4.
FIG. 2 shows another form of the dither circuit according to the prior art. In this second prior art apparatus, preset switches 7, 8, 9 and 10 are omitted. Instead, a dither pattern is previously written in a read only memory (ROM) to carry out systematic dither. Like reference numerals to FIG. 1 represent the same and corresponding elements.
Element 18 is a ROM for dither matrix. The memory capacity required for ROM 18 is, in the shown example, 4 bit. The numbers of bits z of the output line of ROM 18, that is, dither signal 6 may be equal to or less than the number of bits n of the output 3 from A-D converter 2. The sum of the number of bits y of the horizontal address control line 16 and the number of bits x of the vertical address control line 17 may be set to be equal to or more or less than the number of bits n of the output 3 from A-D converter 2. However, representation of the maximum gradation at the minimum cost is possible only when n=Z=(X+y)
The prior art systems described above have the previously mentioned drawbacks.